1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRAM) with an array of cascade dynamic memory cells capable of storing bits of information in bits.
2. Description of the Related Art
DRAM cells now in practical use are made up of a transfer gate MOS (Metal-Oxide-Semiconductor) transistor connected to a word line and a bit line and an information-storing capacitor connected to this transistor.
In connection with this, the applicant of this invention has proposed cascade gate semiconductor memory cells, for example, as shown in FIGS. 1 and 2, in U.S. Pat. application Ser. No. 687,687.
The DRAM cell of FIG. 1 contains cascade-connected MOS transistors Q1 to Q4 and information-storing capacitors C1 to C4 one end of which is connected to one end of each of transistors Q1 to Q4. By performing on/off control of transistors Q1 to Q4 in a specified sequence, stored information is sequentially read to the node N1 from capacitors C1 to C4, starting with capacitor C1 nearest one end of the cascade connection (read/write node N1). It is also possible to sequentially write information at node N1 into capacitors C4 to C1, beginning with C4 farthest away from node N1.
The DRAM cell of FIG. 2 is such that an additional MOS transistor Q5 is connected between one end of DRAM cell transistor Q4 of FIG. 1 and a second node N2. By performing on/off control of transistors Q1 to Q5 in a specified sequence, stored information is sequentially read to the node N1 from capacitors C1 to C4, starting with capacitor C1 nearest the node N1. It is also possible to sequentially write information at node N2 into capacitors C1 to C4, beginning with C1 nearest node N1.
Cascade-gate memory cells as shown in FIGS. 1 and 2 can store bits of information in bits. An array using these cells requires only one connection between a memory cell and a bit line for every specified number of bits, which results in much higher packing density than that of a conventional DRAM with an array of one-transistor one-capacitor cells, thereby reducing the price per bit remarkably.
With a DRAM with the aforementioned cascade-gate memory cells, because the information stored in the cell is lost as a result of destructive reading, it is always necessary to rewrite the original information in it. Since the reading and writing order for the capacitors in one memory cell is determined, it is impossible to rewrite the information into a given capacitor immediately after it has been read from that capacitor. That is, rewriting into a given capacitor from which the information has been read is impossible until the succeeding capacitors within the same cell have been read from.
For this reason, when a DRAM is constructed using an array of aforementioned cascade-gate memory cells, a means is necessary which can sequentially rewrite (or write) the information after multiple bits have been read from the memory cells in time sequence.
In this connection, the applicant of this invention has proposed, in U.S. Pat. application Ser. No. 721,255, a semiconductor memory device that contains a storing means for temporarily storing bits of information read in time sequence from the memory cells and is able to sequentially rewrite (or write) the bits of information after the reading has finished.
It may be possible to construct a DRAM where a group of memory cells in a column of an array of cascade memory cells is accessed serially, making use of the ability of the above-mentioned cascade memory cells to be accessed serially. This construction, however, requires improvements in the method of rewriting the information read in time sequence from the cascade memory cells.